The present invention relates generally to the field of integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of shallow trench formation to eliminate residual material or xe2x80x9cpoly stringerxe2x80x9d with controlled step height and corner rounding.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Different isolation techniques are utilized to provide electrical isolation between devices fabricated on the same piece of silicon. One isolation technique is local oxidation of silicon (LOCOS). LOCOS is often employed to electrically insulate or isolate various portions or structures of the semiconductor device from other portions of the device. Another isolation technique for isolating devices of the same type is shallow trench isolation (STI).
Conventional STI formation uses a thick layer of nitride as a hard mask. The nitride thickness depends on the litho printing capability, normally at the range of 1400-1800 angstroms (xc3x85). This nitride layer or hard mask provides a chemical-mechanical polish (CMP) stop layer for the oxide gap material, which is removed after trench oxide gap fill. After the nitride layer is removed, an uneven formation or relatively large step may e created on the top surface of the substrate. The large step is due to the height of the oxide gap fill which generally has the same height as the nitride layer. Disadvantageously, residual material or xe2x80x9cpoly stringerxe2x80x9d from subsequent deposition, masking, and photolithographic steps can form along the large step. Failure to remove this material can lead to unwanted electrical shorting paths between adjacent lines.
Thus, there is a need for a method of shallow trench formation with reduced poly stringer problems. Further, there is a need for a method of shallow trench isolation formation with controlled step height and corner rounding. Even further, there is a need for an integrated circuit manufactured by a technique in which the mask layer used in shallow trench isolation formation is thinner than conventional mask layer.
An exemplary embodiment is related to a method of fabricating an integrated circuit including multiple devices and isolation structures separating the multiple devices. This method includes depositing a mask layer with a first thickness above a semiconductor substrate, forming an aperture in the mask, and trimming the mask layer to a second thickness where the second thickness is less than the first thickness.
Briefly, another exemplary embodiment is related to an integrated circuit including at least two isolation structures on a common semiconductor material. The integrated circuit is manufactured in a process including providing a mask layer with a first thickness over a semiconductor substrate, selectively creating a trench in the semiconductor substrate, and thinning the mask layer to a second thickness. The second thickness is less than the first thickness.
Briefly, another embodiment is related to a method of manufacturing an integrated circuit including the steps of (a) performing a shallow trench isolation etch to form a trench in a substrate, an oxide liner proximate the trench and disposed over the substrate, and a mask layer disposed over the oxide liner; and (b) trimming the mask layer.
Other principle features and advantages of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.